Lea Verou, PhD @lea.verou.me I make things for making things.
@leaverou@front-end.social on Mastodon, @leaverou elsewhere
https://lea.verou.me
David Buchanan @retr0.id reverse engineering, cryptography, exploits, hardware, file formats, and generally giving computers a hard time
Fedi: @retr0id@retr0.id
Macroblog: https://www.da.vidbuchanan.co.uk/blog/
Bryan Cantrill @bcantrill.bsky.social Co-founder and CTO of Oxide Computer Company. According to Field of Schemes, "tech exec and Oakland A's fan" -- but more of an Oakland Ballers fan now.
hforsten @hforsten.com Electrical engineer. RF electronics, IC design, radars, FPGA, programming. hforsten.com
Jan Gray @jangray.bsky.social Kilocore RISC-V FPGA accelerators; former Microsoft dev tools architect; RISC-V SoftCPU SIG & Composable Custom Extensions Task Group; blog: https://fpga.org. Cyclist. Let's try kindness. 🇨🇦-🇺🇸. On hiatus! Be well.
Kevin Hubbard @khubbard.bsky.social Electrical Engineer. ASICs, FPGAs, Python.
Fan of convertibles and 6502 CPUs.
Author of Mastering FPGA Chip Design : For Speed, Area, Power, and Reliability.
Seattle,WA,US,Earth,Sol,MlkyWy
https://blackmesalabs.wordpress.com/
Piotr Esden-Tempski @esden.net fediverse: @esden@chaos.social
Embedded Open-Source Hacker? Founder of 1BitSquared https://1bitsquared.com | Maintainer https://black-magic.org | https://icebreaker-fpga.org
#hardwarehackers #fpga #asic #embedded #risc-v
he/him
Ken Shirriff @righto.com Computer history. Reverse-engineering old chips. Restored Apollo Guidance Computer, Alto. Ex-Google, Sun, Msft. So-called boffin.
Matt Venn @mattvenn.net Engineer and Technology Communication. On a mission to make ASICs more accessible. YosysHQ & Tiny Tapeout founder member.
https://ZeroToASICcourse.com
https://TinyTapeout.com
Greg @gregdavill.bsky.social Electronics engineer. RISC-V ASICs at IQonIC Works 🧙♂️ (He/Him)
I also take macro photos of electronics
Bluesky @bsky.app official Bluesky account (check username👆)
Bugs, feature requests, feedback: support@bsky.app