Epholys

@epholys.bsky.social

29 Followers 289 Following

Graph visualization of a 4-Way 16-bit wide Multiplexer. The graph is an absolute mess: nands placed haphazardly, edges crossing everywhere, jumbled inputs and outputs.
Black and white image representing the individual bits of an encoding of logic gates.
A screenshot of a tiny web app. There's a counter at the top of the screen, which is at 8. A button + next is next to it. There's a list of 8 dates below these two, which are set to some time during this day, like 9h33 or 18h07. A Save button is also present, at the right
Diagram graph that represents a full-adder, with nested components that end with the universal NAND gate
Graph of a half-adder logic circuit, showing nested logic gates until the base nand gates