Flow Computing

@flow-computing.bsky.social

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Speed is the superpower of computing. Our Parallel Processing Unit (PPU) gives CPUs a significant performance boost. 💻 Learn more: https://flow-computing.com

Animated explainer showing how Flow PPU automatically offloads explicitly parallel parts of an application while sequential code remains on the CPU. The animation highlights sections of code, illustrating how sequential and parallel components integrate into a single program. Diagram adapted from Flow Computing's software architecture presentation.

View from an airplane window above the clouds during sunrise, with a vibrant orange horizon stretching across the sky on the journey to Oulu for leadership strategy sessions.

Flow Computing carousel cover slide with the headline: "Adding more CPU cores doesn't produce linear performance scaling." Subheading: "Measured performance on a 96-core AMD EPYC™ Zen5 processor shows how real-world scaling diverges from the theoretical ideal." A hand-drawn arrow at the bottom indicates there is another slide.

Promotional graphic for Arctic15 2026 in Helsinki featuring a black-and-white portrait of Flow Computing CEO and Co-Founder Timo Valtonen on a blue technology-themed background. The graphic includes the text “I'm Attending Arctic15 – 15th Anniversary Edition” and Arctic15 event branding.

Minimalist grey title slide with Flow branding. Large black text reads: “The Parallel Processor T

Marcello Ranone, Head of CPU Development at Flow Computing, speaking to computer architecture students at Politecnico di Torino. A presentation slide reading “Engineering: A Team Sport” is projected above him as he discusses engineering collaboration, careers in CPU design, and professional growth.

Black-and-white portrait of Flow Computing CEO & Co-Founder Timo Valtonen with the headline ‘Meet Timo.’ Timo will represent Flow Computing at upcoming deep tech events and meet with investors, partners, and industry leaders.

Black-and-white photo of a Deep Tech Momentum (DTM26) High-Performance Computing plaque displayed in Berlin, recognizing participation in the DTM100 pitch competition on May 20–21, 2026.

A minimalist grayscale graphic with a blurred bar chart in the background and the words “VALIDATED,” “MEASURED,” and “SIGNIFICANT” spaced across the top. Centered over the chart is an eye-with-a-slash icon above bold text reading “COMING SOON” and smaller text reading “New performance results.” The word “FLOW” appears at the bottom center. The design suggests upcoming benchmark or performance data that is not yet publicly visible.

A technical architecture diagram labeled “FLOW” illustrating the Flow Computing architecture and data flow between CPU and PPU components. The diagram shows a distance-aware network connected to CPU cache and shared CPU data memory at the top, linked to multiple processing units and low-overhead multithreading layers. Below is a high-bandwidth synchronous network connecting distributed shared PPU data memory blocks. Additional annotations highlight features such as low-cost synchronization, flexible threading (“Flexible T”), no empty slots, and computation executed only once per thread control flow (TCF). The design emphasizes scalable parallel processing, synchronized communication, and efficient shared-memory execution.

Black-and-white photo of the Flow Computing team gathered around a long dinner table at a restaurant during the Italy face-to-face week.

Diagram titled “Flow PPU-enhanced CPU” showing a hybrid computing architecture. On the left, a stacked multi-core CPU block labeled “CPU” contains text reading “Arm, Power, RISC-V, x86 core” and “Low-latency SMP/NUMA architecture.” On the right, a separate block labeled “Parallel Processing Unit (FLOW PPU)” contains text reading “Multicore Parallel Processing Unit” and “High throughput ESM architecture.” A large two-way arrow between the CPU and Flow PPU indicates tight coupling and communication. Both connect downward via arrows to a shared “External Shared Memory System” at the bottom of the diagram. The layout illustrates how the CPU and Flow PPU work together within a unified shared-memory architecture.

Diagram showing ‘Single Thick Control Flow’ with synchronized parallel processing over time across multiple processors.

Diagram showing the Flow PPU (Parallel Processing Unit) as a 64-core general-purpose parallel co-processor integrated alongside a CPU on a chip. The visual highlights that it unlocks scalable parallel performance, is instruction-set independent, and works with existing CPU architectures. Additional text explains it is a licensable IP block with its own software and compiler, designed to scale CPU performance while remaining backward compatible.

Black-and-white graphic featuring robotic arms in the background with a centered white paper-style overlay. Large text reads: “just a little reminder: scalable parallel execution drives real-time sensor & signal processing.” Smaller text around the edges references robotics systems, real-time control, parallel workloads, and notes that traditional multicore CPUs struggle to scale efficiently, while Flow enables scalable parallel execution for real-time data processing.

Three men standing outdoors take a selfie in front of a residential home with a garden and trees, captured on a bright, sunny day.

Simple diagram titled “Newcomer’s guide to Flow PPU” showing: (1) the problem—CPUs struggle to efficiently utilize parallel workloads, (2) Flow PPU as a general-purpose parallel co-processor alongside the CPU, (3) how it works—CPU handles sequential tasks while PPU executes parallel workloads, and (4) why it matters—improved parallel execution increases overall system throughput.

Podcast graphic with three speakers discussing how microprocessor innovation has become incremental and why general-purpose parallelism is a key future direction.

Minimalist graphic with the title “FLOW PPU” and key descriptors: “general-purpose parallel processing CPU co-processor” on the left, and “linear scaling,” “low synchronization,” and “instruction set independent” on the right, highlighting core architectural features of Flow PPU.

Minimal grey graphic featuring the statement “EDGE AI NEEDS PARALLELISM” centered inside a circular outline with Flow branding below. The visual emphasizes the importance of parallel computing for enabling efficient AI workloads on edge and consumer devices.

Black-and-white portrait of Flow Computing founders Dr. Martti Forsell, Timo Valtonen, and Jussi Roivainen standing together. The graphic headline reads “Meet the Founders of Flow” with text below noting their visit to Silicon Valley, California from March 19–27, 2026.

Conference photo from World RISC-V Days in Turin featuring Flow Computing Head of CPU Development Marcello Ranone presenting Flow’s approach to scalable parallel performance.

Minimal grey quote card featuring a statement from FOV Ventures’ “Europe’s Deep Tech Frontier” article describing Flow Computing as a research-driven company building a new chip architecture to accelerate parallel computing for real-time AI in physical systems. The graphic includes the FOV Ventures attribution and Flow branding.

Animated diagram illustrating research foundations behind Flow’s architecture. The visual references Thick Control Flow (TCF), a programming and execution model for coordinating parallel fibers across processors to improve synchronization efficiency and scalability. The animation highlights how tasks branch and synchronize within the model, demonstrating concepts used to enable scalable parallel execution in the Flow PPU architecture.

Close-up illustration of a processor on a circuit board. Text explains that overall performance depends on CPU-side parallelism, data preparation, pipeline efficiency, synchronization, and throughput per watt. Source: Arm / Futurum Research, 2026.

Black-and-white four-panel portrait collage of Flow team members with quotes about building an international engineering team across Europe. Center badge reads “Parallel Perspectives - Flow.” Text highlights attracting talent across Europe and scaling collaboration efficiently.

Flow Computing team members sitting together on a sofa in a modern office lounge, smiling toward the camera in a collaborative workspace environment.

KPMG Private Enterprise Global Tech Innovator 2025 title screen introducing the interview featuring Flow Computing.

Black-and-white group photo of Flow Computing founders and team leads gathered during an in-person alignment session in Oulu, Finland.

Diagram-style graphic with the text “Flow PPU is designed to integrate with CPUs across instruction sets,” with logos for Arm, AMD, Intel, RISC-V, and OpenPOWER shown as example CPU ecosystems, highlighting Flow’s instruction-set-independent PPU architecture.

Flow CEO standing in front of Finland’s Startup Hall of Fame wall at Maria 01, with the Flow ‘Rising Star of the Year 2025’ badge highlighted among notable Finnish startups.

Stylized image of a CPU integrated into a circuit board, with illuminated data paths emphasizing system architecture, overlaid with the text “Performance is an architectural decision.”

Flow Computing “In the headlines” section showing four media mentions: Vestbee lists Flow among its 100 must-follow startups from Winter Pitch; Talouselämä names Flow among the 10 most interesting startups of 2025; StartUs Insights includes Flow among AI supercomputing startups to watch; and EU-Startups features Flow in “The next wave of Finnish innovation.

Timo Valtonen wearing a Flow hoodie takes a selfie in front of a large illuminated ‘SLUSH’ sign at the Slush event. The photo is in black and white.