anxietism

@merci.chaton.lol

104 Followers 421 Following

I love life andculture and the java 21 programming language

emuTOS showing a useful dialog "PRINTER is a printer" after double clicking the printer
airbus beluga XL
bomberman hero ost CD release cover view its printed to looks likewas blown by a bomb
a youtube video titled i cant stop drinking and smoking its killing me
Mary Jo’s Rules1 Avoiding pipeline stalls in software can be accomplished by understanding the following rules. 1. VU register destination writes 4 cycles later (need 3 cycles between load and use). This applies to vector computational instructions, vector loads, and coprocessor 2 moves (mtc2). 2. SU register load takes 3 cycles (need 2 cycles between load and use). This applies to SU loads and coprocessor moves (mfc0, cfc2, mfc2). SU computational results are available in the next cycle (see “SU is Bypassed” on page 44). 3. Any load followed by any store 2 cycles later, causes a one cycle bubble. Coprocessor moves (mtc0, mfc0, mtc2, mfc2, ctc2, cfc2) count as both loads and stores. 4. A branch target not 64-bit aligned always single issues. 5. Branches: a. Can dual issue (with preceding instruction). b. No branch instruction permitted in a delay slot. c. Delay slot always single issues. d. Taken branch causes a 1 cycle bubble. Register Hazards The RSP hardware implements register hazard locking for SU and VU registers. Once an instruction is fetched and decoded, its destination register is marked as a “hazard”; if this register is used as an input to a subsequent instruction, the pipeline will stall.
spider steve
Gas above 2 euros per liter :(
corporate memphis illustration for culture amp with the phrase "lets create a better world of work"
Albert Wesker from Resident Evil