Home [Unofficial] @riscv.org.web.brid.gy RISC-V is an open standard Instruction Set Architecture (ISA) enabling a new era of processor innovation through open collaboration.
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Carlos de Paula @carlosedp.com RISC-V Ambassador, cloud architect and developer.
I've build multiarch Kubernetes clusters, wrote a RISC-V processor, made a K8s operator and play with multiple programming languages like Scala, Erlang, Go and many more.
Flux @willflux.bsky.social Only hardware makes it possible!
FPGA, RISC-V, 68K, OS, graphics, demos, permacomputing
http://projectf.io | http://systemtalk.org
kazu42 @kazu.bsky.social B2 ๅ
ผ SWE(R&D)๏ผ ๅ็ป้
ไฟกใฎไผ็คพ ๅ
ผ 42Tokyo 2021/10/ใ ใปC/C++/Rust/Go/Lua/Swift/OCaml ่ชไฝใใ๏ผCPU/OS/ใณใณใใคใฉ/shell/Git/editor... interest๏ผReact/RISC-V/Network
Claire Xen ๐ณ๏ธโโง๏ธ ๐ง๐ปโโ๏ธ ๐๐๐ @clairexen.bsky.social Neurodiverse Trans Geek Girl ๐งโโ๏ธ
Queer Kinky Poly Mess ๐ณ๏ธโ๐ ๐ณ๏ธโโง๏ธ
CTO @YosysHQ ๐บ RISC-V, SMT ๐ฉโ๐ป
Opinions are my Ceti eel's ๐
ACAB BLM โ I am Antifa ๐ด๐ฉ
Vienna, Austria ๐ she/her ๐งโโ๏ธ
Olof Johansson @olofj.bsky.social Natural habitat: Kernel +/- 2 layers. Recovering maintainer.
Generally excited about RISC-V. Previously: Software at Tenstorrent.
Piotr Esden-Tempski @esden.net fediverse: @esden@chaos.social
Embedded Open-Source Hacker? Founder of 1BitSquared https://1bitsquared.com | Maintainer https://black-magic.org | https://icebreaker-fpga.org
#hardwarehackers #fpga #asic #embedded #risc-v
he/him
Jan Gray @jangray.bsky.social Kilocore RISC-V FPGA accelerators; former Microsoft dev tools architect; RISC-V SoftCPU SIG & Composable Custom Extensions Task Group; blog: https://fpga.org. Cyclist. Let's try kindness. ๐จ๐ฆ-๐บ๐ธ
Riscy @riscy.bsky.social Half Life, RISC-V & Miata appreciator
Alex Bradbury @asbradbury.org Compilers at Igalia. @llvmweekly.org author. Mostly RISC-V, LLVM, and a little WebAssembly. Previously lowRISC CTO and co-founder. Blogs at https://muxup.com
Bluesky @bsky.app official Bluesky account (check username๐)
Bugs, feature requests, feedback: support@bsky.app